1. Field of the Invention
The invention relates to television tuners, and more particularly, to a double conversion television tuner used to process a received RF signal.
2. Description of the Prior Art
One of the most significant costs in television manufacturing is the cost of the tuner. Furthermore, with the increasing desire to integrate TV functions into personal computer (PC) systems and other electronic devices, the cost of the tuner needs to be reduced. TV tuners may be fabricated on circuit boards and then installed in personal computer systems, thereby allowing the PC to function as a television set. These tuners convert a radio frequency television signal into a baseband (or low frequency) video signal, which can then be passed on to other elements in the PC for video processing applications.
FIG. 1 shows a highly integrated television tuner 100 disclosed by U.S. Pat. No. 5,737,035. The television tuner 100 includes an adjustable low noise amplifier 101, a first mixer 102, a first local oscillator 104, a band-pass filter 106, a second mixer 108, being an image rejection type mixer, a second local oscillator 110, a first intermediate frequency amplifier 112, a second band-pass filter 114, and a variable intermediate frequency amplifier 116.
FIG. 2 shows a frequency domain plot of a filtered intermediate frequency signal 109 in FIG. 1. By adjusting the frequency of the first local oscillator 104, a selected carrier frequency in the received RF signal is positioned in the first intermediate frequency signal (IF1) at 1220 MHz. This desired signal is allowed to pass through the band-pass filter 106, which has a center frequency of 1220 MHz, and results in the desired signal 200 shown in FIG. 2. The desired signal 200 is then mixed by the second mixer 108 with a reference signal (LO) from the second local oscillator 110 at 1176 MHz to produce an output signal at 44 MHz. However, the second local oscillator 110 also mixes an image signal 202 located at 1132 MHz with the 1176 MHz reference signal, and this too produces an output signal at 44 MHz. In other words, both the desired signal 200 and the image signal 202 are located in the output 111 of the second mixer 108 at 44 MHz.
In order to prevent the image signal 202 from interfering with the desired signal when mixed with the second mixer 108, the power level of the desired signal P1 should be higher than the power level of the image signal P2 before entering the second mixer 108. For example, a typical image attenuation requirement specifies the image signal 202 be at least 50 dB below the desired signal 200. As the image signal 202 is only 88 MHz away from the desired signal 200, it is very difficult to build the band-pass filter 106 with such a sharp fall-off. For this reason, the second mixer 108 is required to be an image rejection type mixer in order to prevent the image signal 202 from appearing in the output 111 of the second mixer 108.
FIG. 3 shows a Hartely architecture image rejection mixer 300 as described by Razavi on pages 139 to 144 of the textbook “RF Microelectronics”. The Hartely architecture image rejection mixer 300 receives the filtered intermediate frequency signal 109 and includes a first mixer 302, a first low-pass filter 304, a 90° phase-delay unit 306, a second mixer 308, and a second low-pass filter 310. The output of the 90° phase-delay unit 306 and the second low-pass filter 310 are added by an adder 312 to form the output 111 of the mixer.
Although the Hartely architecture image rejection mixer 300 prevents the image signal 202 from appearing in the output 111, the Hartley architecture image rejection mixer 300 increases the overall design complexity of the tuner; increases the power consumption of the tuner due to using two mixers 302, 308; and because the filtered intermediate frequency signal 109 is first divided into in-phase I and quadrature Q signal paths using the first mixer 302 and the second mixer 308, if there is any mismatch caused by the 90° phase-delay unit not being exactly 90°, the Hartely architecture image rejection mixer 300 also results in decreased performance due to incomplete image rejection and/or gain mismatch between the two paths. This mismatch between the two paths is especially serious for signals such a digital TV signals which have a very strict QAM256 I, Q mismatch requirement.
Razavi, on pages 144 to 146 of the textbook “RF Microelectronics”, also describes a Weaver architecture image rejection mixer, which is another image rejection mixer architecture used in the prior art. The Weaver architecture replaces the 90° phase-delay unit 306 with a second a second quadrature mixing operation, which performs the same function as the 90° phase-delay unit 306. However, the Weaver architecture image rejection mixer shares the same problems as the Hartely architecture image reject mixer 300, specifically: increased overall design complexity, increased power consumption, and incomplete image rejection due to gain and phase mismatch.